We're a small, founder-led engineering house looking for people who care about doing precise, meaningful work — from RTL to tapeout to orbit.
At Genic Semiconductor, every engineer works close to the silicon and close to the client. There are no account-manager layers and no black-box handoffs — you own real architecture decisions from day one.
We're building for AI, space and next-generation secure networking. If you want your work to matter at the transistor level, this is a team worth joining.
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Work on real architecture and verification decisions from day one — not tickets handed down from a black box.
Most roles support remote or hybrid work, with async-friendly collaboration across our engineering team.
Work alongside senior engineers on UVM, RISC-V, post-quantum cryptography and space-grade systems.
Market-competitive pay for the region, tied to skill and ownership rather than tenure alone.
We care about outcomes and coverage closure — not hours logged at a desk.
Ship work that ends up in AI accelerators, secure networking silicon and CubeSats in orbit.
Don't see an exact match? Scroll down — we always want to hear from strong engineers.
Design and implement RTL for custom and configurable silicon — from microarchitecture through synthesis-ready code, working closely with our verification team.
Apply NowBuild constrained-random, coverage-driven UVM testbenches and own verification signoff for ASIC and SoC projects headed to tapeout.
Apply NowDevelop low-level firmware and bring-up software for custom and configurable RISC-V cores, from embedded controllers to multicore compute.
Apply NowDesign and harden post-quantum cryptographic cores and secure interconnect IP for networking and defense-adjacent silicon.
Apply NowEngineer radiation-aware compute and communication subsystems for CubeSat and small-satellite missions, from design through validation.
Apply NowOwn synthesis, place & route and timing signoff across leading-edge nodes, including chiplet and UCIe packaging flows.
Apply NowWe review every application personally — no automated filters deciding who gets seen.
A focused conversation about your experience and a practical problem relevant to the role.
A deeper technical session with the engineers you'd actually work alongside.
Clear terms, a direct start date, and a mentor assigned from week one.
We're always glad to hear from strong ASIC, verification and security engineers — send us your background anyway.